Massively parallel neural interfaces with thousands of recording channels generate bursty event traffic that can easily deadlock on-chip interconnects if buffers saturate. This engineering paper proves the formal safety of virtual-channel dimension-order routing (DOR) architectures optimized for neural spikes.
By multiplexing physical links across independent virtual channels, event packets blocked by downstream congestion do not stall packets destined for orthogonal mesh coordinates, mathematically eliminating circular dependency cycles.
Synthesized in 22nm Fully Depleted Silicon-on-Insulator (FD-SOI) technology, each 5-port asynchronous router occupies only 0.012 mm² of silicon area and leaks less than 450 nanowatts of standby power.